Tuesday, April 16, 2002

Hammer Analysis
By Nils Dahl
Date: October 17, 2001


I just reviewed the 45 page Hammer processor pdf file that got released late Monday. I am halfway between a nasty giggle and a full out roar of hilarity.
Ah, there will be lots of people doing lots of very fine reviews of the new Hammer architecture. I mean - an 8-way system that can take 64 DDR SDRAM DIMMS (8 modules per node) is very close to a ...
Well, let me spell it out. The real key to Hammer is three HyperTransport interfaces, one being a dedicated interface to fast I/O. There is one for I/O and two more for communication between processors. Yeah, super-high speed parallel links between processors.
This is much closer to a very fancy minicomputer than to the good old Xeon with its backside cache. This is a basic scheme for a small supercomputer that can handle certain special types of work very nicely.
Er, breaking encryption for example. Maybe sharing loads dynamically for rapid generation of 3D objects and scenes - a field that once was the province of high end manufacturing firms that wanted a 3D cad animation of complex assemblies in action but now is widely used in movies and other neat stuff.
Think of it as an Inmos Transputer on steroids. With AMD's new Hammer scheme, one processor can be handling the retrieval of data from hard drives and then pass this directly on to another processor that is generating web pages or doing movie effects processing

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